Liquid crystal display devices become display terminals of mobile communication devices, computers, televisions, etc, because of advantages of high display quality, low price and portability. A generally used technology for driving a panel of a liquid crystal display device for a television is a gate driver on array (GOA) technology. In the GOA technology, a driving circuit of horizontal scanning lines of a panel is manufactured on a substrate around a display area by using an original process for manufacturing a flat display panel. By means of the GOA technology, the process for manufacturing the flat display panel can be simplified, and a bonding procedure in a horizontal scanning line direction is not needed. In this way, productivity can be improved, and cost of products can be reduced. Besides, integration degree of a display panel can be improved, so that the display panel is more suitable for manufacturing narrow-bezel or no-bezel display products so as to satisfy pursuit in vision of modern people.
In the liquid crystal display device, each pixel comprises a thin-film transistor (TFT). A gate of the thin-film transistor is connected to a scanning line, a drain thereof is connected to a data line, and a source thereof is connected to a pixel electrode. When a sufficient voltage is applied to a scanning line, all thin-film transistors on the scanning line can be turned on. At this time, a display signal voltage on a data line is written into a pixel so as to control transmittance of light of different liquid crystals and further achieve color control.
An existing GOA circuit generally comprises multiple GOA units in cascade connection. Each stage of GOA unit is configured to drive a corresponding stage of scanning line. A GOA unit mainly comprises a pull-up part, a pull-up control part, a transfer part, a key pull-down part, and a pull-down holding part and a boost capacitor which is configured to boost an electric potential. The pull-up part is mainly configured to output a clock signal as a gate signal. The pull-up control part is configured to control turn-on time of the pull-up part, and is generally connected with a transfer signal or a gate signal transmitted from a previous-stage GOA unit. The pull-down part is configured to pull down a gate signal to a low level as soon as possible, i.e., to turn off the gate signal. The pull-down holding part is configured to maintain a gate output signal and a gate signal of the pull-up part in a turn-off state. Generally, two pull-down holding parts are provided, and they function alternately. The boost capacitor is configured to boost a voltage at node Q for a second time, which is beneficial for outputting a G(N) signal of the pull-up part.
FIG. 1 shows a connection mode of multiple stages of a GOA circuit used in a flat display device in the prior art. In FIG. 1, metal wires of a first low-frequency clock signal LC1, a second low-frequency clock signal LC2, a direct-current low voltage VSS and four high-frequency clock signals CK1 to CK4 are provided at peripheries of the GOA circuit at left and right sides of a panel. A plurality of data lines for providing data signals, a plurality of scanning lines for providing scanning signals and a plurality of pixels P which are arranged in array are disposed. Each pixel P is electrically connected to one data line and one scanning line. A plurality of shift registers, i.e., S(N−3), S(N−2), S(N−1), and S(N) (which are not shown in FIG. 1), are arranged sequentially. Each of the shift registers is configured to output a gate signal for scanning a corresponding scanning line in a display device, and respective shift registers are electrically connected to the first low-frequency clock signal LC1, the second low-frequency clock signal LC2, the direct-current low voltage VSS and one high-frequency clock signal of the four high-frequency clock signals CK1 to CK4.
Specifically, an Nth-stage GOA circuit receives the first low-frequency clock signal LC1, the second low-frequency clock signal LC2, the direct-current low voltage VSS, one high-frequency clock signal of the four high-frequency clock signals CK1 to CK4, a G(N−2) signal and a turn-on signal ST(N−2) generated by an (N−2)th-stage GOA circuit, and a G(N+2) signal generated by an (N+2)th-stage GOA circuit respectively, and the Nth-stage GOA circuit generates G(N), ST(N), and Q(N) signals.
However, the voltage at node Q of the above GOA circuit is low, and therefore driving performance of the GOA circuit is not high.